Gallium Nitride-on-Silicon (GaN-on-Si) power devices are affected by a parasitic conductive layer at an interface between the Si and the III/Nitride stack, which increases the buffer leakage current and reduces the breakdown voltage. This detrimental conductive path can be interrupted by removing the Si substrate, globally over the entire wafer, as described in, for example, “Silicon Substrate Removal of GaN DHFETs for enhanced (>1100V) Breakdown voltage,” P. Srivastava et al., IEEE Electron Device Letters 31 (8), pp 851-853, 2010. Alternatively, the detrimental conductive path can be interrupted by removing the Si substrate selectively at specific locations, as described in, for example, “Si trench around drain (STAD) technology of GaN-DHFETs on Si substrate for boosting power performance,” P. Srivastava et al., Proc. International Electron Devices Meeting (IEDM) 2011. Si removal has been proven to increase the breakdown voltage without increasing the buffer thickness. Moreover, a significant reduction of the buffer leakage current at high temperature has been reported with this technology, as shown in the second of the previously cited references.